The inventors of the present invention have already proposed a marching-memory computer organization encompassing a processor and a new main memory called “a marching main memory” (See WO 2011/010445A1). The processor of the proposed marching-memory computer recited in WO 2011/010445A1 includes a control unit having a clock generator configured to generate a clock signal and an arithmetic logic unit configured to execute arithmetic and logic operations synchronized with the clock signal. In addition, the proposed marching main memory encompasses an array of memory units, usually called locations. Each of the memory units has a unit of information of byte size or word size and input terminals of the array and output terminals of the array. The proposed marching main memory stores information in each of the memory units and transfers synchronously with the clock signal, step by step, toward the output terminals, so as to provide the processor with the stored information actively and sequentially so that the arithmetic logic unit can execute the arithmetic and logic operations with the stored information. In addition, the results of the processing in the arithmetic logic unit are sent out to the marching main memory, except that in case of instructions movement, there is only one way of instructions flow from the marching main memory to the processor.
In accordance with the marching-memory computer architecture, recited in WO 2011/010445A1, because each of the memory units in the array of memory units, which implement the marching main memory, has a sequence of bit-level cells so as to store information of byte size or word size, the information of byte size or word size is transferred along the horizontal data-transfer lines synchronously with clock signals, step by step, and therefore random access operation of the individual bit-level cells is not required in the marching main memory. Then, since bottlenecks ascribable to wirings between processor chips and the conventional main memory chips or conventional cache memory chips, and bottlenecks between all of the units in a parallel processor, these bottlenecks are inherently existing in conventional computer system, can be removed, a very high speed operation with a very low power consumption can be achieved.
In the marching-memory computer proposed in WO 2011/010445A1, the way of transferring information of byte size or word size, which is assisted by clocked AND operation, is proposed as an example. To establish the combinational function of the clocked AND gate, a plurality of transistors is required in each of the bit-level cells and the operation of the marching-memory is accompanied by delays in the clocked AND gate.